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Extendible Translating Instruction Set Simulator (ETISS)
- Project
- 16018 COMPACT
- Type
- New standard
- Description
- Instruction Set Simulator extendible by timing models
- Advanced SW performance profiling
- Contact
- Daniel Mueller-Gritschneder
- daniel.mueller@tum.de
- Technical features
Input(s):
- Embedded SW
- Pipeline Description
Main feature(s):
- Simulation environment for Embedded SW (Instruction Set Simulator)
- Focus: RISC-V processors
Output(s):
- SW profiling information
- Integration constraints
- Out-of-the-box Support for RISC-V
- Other processor ISAs need additional modeling effort
- Targeted customer(s)
- SoC architects
- Embedded SW developers
- Conditions for reuse
- ETISS open source available – BSD license
- Github link: https://github.com/VP-Vibes
- Confidentiality
- Public
- Publication date
- 08-12-2020
- Involved partners
- Technical University of Munich (DEU)